The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to a thin channel-on-insulator metal oxide semiconductor field effect transistor (MOSFET) device having an n+ epitaxy substrate with an embedded stressor.
In the manufacture of integrated circuit devices it is desirable to reduce the dimensions of the transistors used to form the individual circuits. In the case of field effect transistors (FETs), reducing the channel length provides the capability to deliver a given amount of drive current with a smaller channel width. By reducing the width and length of a FET, the parasitic gate capacitance (which is a function of the area defined by the width and length) can be reduced, thereby improving circuit performance. Similarly, reducing the size of transistors is beneficial in that less area is consumed for a given circuit, and this allows more circuits in a given area, or a smaller, less costly chip, or both.
To further enhance transistor performance, MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for n-channel (NFET) or for p-channel (PFET) devices. Generally, it is desirable to induce a tensile strain in the n-channel of an NFET in the source-to-drain direction to increase electron mobility and to induce a compressive strain in the p-channel of a PFET in the source-to-drain direction to increase hole mobility. Currently, there are several existing approaches of introducing strain in the transistor channel region.
In one approach, strain in the channel is introduced by creating a recess in the substrate in the source/drain regions. For example, a PFET device having a compressive stress in the channel region may be formed on a silicon substrate by epitaxially growing a stress-inducing layer having a larger lattice structure than the silicon, such as a layer of SiGe, within recessed regions in the source/drain regions. Similarly, an NFET device having a tensile stress in the channel region may be formed on a silicon substrate by epitaxially growing a stress-inducing layer having a smaller lattice structure than the silicon, such as a layer of SiC, within recessed regions in the source/drain regions.